Device and circuit-level models for carbon nanotube and graphene nanoribbon transistors

Metal-oxide semiconductor field-effect transistor (MOSFET) scaling throughout the years has enabled us to pack million of MOS transistors on a single chip to keep in pace with Moore’s Law. After forty years of advances in integrated circuit (IC) technology, the scaling of silicon (Si) MOSFET has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. The latest technological advancement has led to a low power, high-density and high-speed generation of processor. Nevertheless, the scaling of the Si MOSFET below 22 nm may soon meet its’ fundamental physical limitations. This threshold makes the possible use of novel devices and structures such as carbon nanotube field-effect transistors (CNTFETs) and graphene nanoribbon field-effect transistors (GNRFETs) for future nanoelectronics. The investigation explores the potential of these amazing carbon structures that exceed MOSFET capabilities in term of speed, scalability and power consumption. The research findings demonstrate the potential integration of carbon based technology into existing ICs. In particular, a simulation program with integrated circuit emphasis (SPICE) model for CNTFET and GNRFET in digital logic applications is presented. The device performance of these circuit models and their design layout are then compared to 45 nm and 90 nm MOSFET for benchmarking. It is revealed through the investigation that CNT and GNR channels can overcome the limitations imposed by Si channel length scaling and associated short channel effects while consuming smaller channel area at higher current density

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.RIGHTS : This article is licensed under the BioMed Central licence at http://www.biomedcentral.com/about/license which is similar to the 'Creative Commons Attribution Licence'. In brief you may : copy, distribute, and display the work; make derivative works; or make commercial use of the work - under the following conditions: the original author must be given credit; for any reuse or distribution, it must be made clear to others what the license terms of this work are

Performance Analysis of Montgomery Multiplier using 32nm CNTFET Technology

In VLSI design vacillating the parameters results in variation of critical factors like area, power and delay. The dominant sources of power dissipation in digital systems are the digital multipliers. A digital multiplier plays a major role in a mixture of arithmetic operations in digital signal processing applications hinge on add and shift algorithms. In order to accomplish high execution speed, parallel array multipliers are comprehensively put into application. The crucial drawback of these multipliers is that it exhausts more power than any other multiplier architectures. Montgomery Multiplication is the popularly used algorithm as it is the most efficient technique to perform arithmetic based calculations. A high-speed multiplier is greatly coveted for its extraordinary leverage. The primary blocks of a multiplier are basically comprised of adders. Thus, in order to attain a significant reduction in power consumption at the chip level the power utilization in adders can be decreased. To obtain desired results in performance parameters of the multiplier an efficient and dynamic adder is proposed and incorporated in the Montgomery multiplier. The Carbon Nanotube field effect transistor (CNTFET) is a promising new device that may supersede some of the fundamental limitations of a silicon based MOSFET. The architecture has been designed in 130nm and 32nm CMOS and CNTFET technology in Synopsys HSpice. The analysed parameters that are considered in determining the performance are power delay product, power and delay and comparison is made with both the technologies.The simulation results of this paper affirmed the CNTFET based Montgomery multiplier improved power consumption by 76.47% ,speed by 72.67% and overall energy by 67.76% as compared to MOSFET-based Montgomery multiplier

Ballistic mobility and saturation velocity in low-dimensional nanostructures

Ohm's law, a linear drift velocity response to the applied electric field, has been and continues to be the basis for characterizing, evaluating performance, and designing integrated circuits, but is shown not to hold its supremacy as channel lengths are being scaled down. In the high electric field, the collision-free ballistic transport is predicted, while in low electric field the transport remains predominantly scattering-limited in a long-channel. In a micro/nano-circuit, even a low logic voltage of 1 V gives an electric field that is above its critical value εc (εnot double greater-than signεc) triggering non-ohmic behavior that results in ballistic velocity saturation. The saturation velocity is an appropriate thermal velocity for a non-degenerate and Fermi velocity for a degenerate system with given dimensionality. A quantum emission may lower this ballistic velocity. The collision-free ballistic mobility in the ohmic domain arises when the channel length is smaller than the mean free path. The results presented will have a profound influence in interpreting the data on a variety of low-dimensional nanostructures

Low-Power And High Performance Of An Optimized FinFET Based 8T SRAM Cell Design

The development of the nanotechnology leadsto the shrinking of the size of the transistors to nanometerregion. However, there are a lot of challenges due to sizescaling of the transistors such as short channel effects (SCEs)and threshold voltage roll-off issues. Fin-Type Field EffectTransistor (FinFET) is another alternative technology tosolve the issues of the conventional MOSFET and increasethe performance of the Static Random Access Memory(SRAM) circuit design. FinFET based SRAMs are faster andmore reliable which are often used as memory cache for highspeed operation. However, 6T SRAM cell suffers from accesstransistor sizing conflict resulting in a trade-off between readand write stability. This paper presents an investigation ofthe stability performance in retention, read and write modeof 22nm FinFET based 8T SRAM cell. The performancecomparison of 22nm FinFET based 6T and 8T SRAMs weremade. The simulation of the SRAM model are carried out inGTS Framework TCAD tool based on 22nm technology. In8T SRAM cell, two n-FinFETs are added to the conventional6T SRAM cell which will be controlled by the Read WordLine (RWL) to isolate the read and write operation path forbetter read stability. FinFET based 8T SRAM cell givesbetter performance in Static Noise Margin (SNM) and powerconsumption than 6T SRAM cells. The simulation resultsaffirms the proposed FinFET based 8T SRAM improvedread static noise margin by 166.67% and power consumptionby 76.13% as compared to the FinFET based 6T SRAM

Hybrid of multi-car elevator system and double-deck elevator system

Multi-car elevator system is a new breakthrough in an elevator system in 2001. It has broken the traditional concept of developing only one elevator car in an elevator shaft. Multi-car elevator system can have more than one elevator car moving in an elevator shaft and it has improved a lot in minimizing the waiting time of passengers if compared with only one elevator car in an elevator shaft. The main advantage of multi-car elevator system is to reduce the construction cost where 30% of the core-tube area of the elevator system is made up of shaft. By developing multi-car elevator system, many of elevator shafts need not to be developed and it still can perform about the same efficiency in serving passengers. However, it is still not able to transport a large number of passengers efficiently if the passengers are calling from the same floor, especially during the up-peak traffic. For that reason, the feature of double-deck elevator system is integrated into multi-car elevator system to develop a new hybridized elevator system called “Hybrid of multi-car elevator system and double-deck elevator system” to solve the limited car capacity problem. The performance of both systems, the hybridized elevator system and the multi-car elevator system is simulated. The result shows that the average journey time of the hybridized elevator system is shorter than the multicar elevator system in all the three traffic modes, i.e. up-peak, down-peak and inter-floor traffics. For the up-peak traffic mode of the hybridized elevator system, it manages to achieve the best result of 33.5% shorter of the average journey time compared to the multi-car elevator system

A review of multi-car elevator system

This paper presents a review of a new generation of elevator system, the Multi-Car Elevator System. It is an elevator system which contains more than one elevator car in the elevator shaft. In the introduction, it explains why the Multi-Car Elevator System is a new trend elevator system based on its structural design, cost saving and efficiency in elevator system. Different types of Multi-Car Elevator System such as circulation or loop-type, non-circulation and bifurcate circulation are described in section 2. In section 3, researches on dispatch strategies, control strategies and avoidance of car collision strategies of Multi-Car Elevator System since 2002 are reviewed. In the discussion section, it reveals some drawbacks of the Multi-Car Elevator System in transport capability and the risk of car collision. There are recommendations to the future work as well

Two-dimensional (2D) transition metal dichalcogenide semiconductor field-effect transistors: the interface trap density extraction and compact model

A surface potential-based low-field drain current compact model is presented for two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductor field-effect transistors that takes into account the effect of interface trap states on device current-voltage (Ids-Vgs) characteristics and transconductance gm. The presence of interface trap states detrimentally affects device Ids-Vgs performance. Minimal work exists on the extraction of trap states (cm-2 eV-1) of MoS2/high-K dielectric/metal-gate stacks. Additionally, there is a lack of compact models for 2D TMD MOSFETs that can take into account the effect of trap states on device Ids-Vgs performance. This study presents a method to extract the interface trap distribution of MoS2 MOSFETs using a compact model. Presented as part of the model is a surface potential/interface trap charge self-consistent calculation procedure and a drain current expression that does not need numerical integration. The model is tested against reported experimental Ids-Vgs data, and excellent agreement is found between the experiment and the model

Performance Evaluation of 14 nm FinFET-Based 6T SRAM Cell Functionality for DC and Transient Circuit Analysis

As the technology node size decreases, the number of static random-access memory (SRAM) cells on a single word line increases. The coupling capacitance will increase with the increase of the load of word line, which reduces the performance of SRAM, more obvious in the SRAM signal delay and the SRAM power usage. The main purpose of this study is to investigate the stability and evaluate the power consumption of a 14 nm gate length FinFET-based 6T SRAM cell functionality for direct current (DC) and transient circuit analysis, namely, in resistor-capacitor (RC) delay. In particular, Berkeley Short-channel IGFET Model-Common Multigate (BSIM-CMG) model is utilized. The simulation of the SRAM model is carried out in HSPICE based on 14 nm process technology. A shorted-gate (SG) mode FinFET is modeled on a silicon on insulator (SOI) substrate. It is tested in terms of functionality and stability. Then, a functional SRAM is simulated with 5 GHz square wave at the input of word line (WL). Ideal square wave and square wave with 100  RC, 5  RC, 1  RC, and 0.5  RC are asserted to the WL and the bit lines (BL&BLB) of SRAM. Voltage at node q and q- is observed. The simulation shows that 1 RC is the minimum square wave that will store correct value in node q and node q-. Thus, this discovery from the research can be used as a modeling platform for circuit designers to explore and improve the SRAM tolerance against RC delay

Automatic human guided shopping trolley with smart shopping system

A shopping trolley is a necessary tool for shopping in supermarkets or grocery stores. However, there are shopping trolleys abandoned everywhere in supermarkets after being used. In addition, there are also shopping trolley safety issues such as sliding down from an escalator. It is known to be an inconvenience and time wasting for customers who are in rush to search for desired products in a supermarket. Therefore, an automatic human and line following shopping trolley with a smart shopping system is developed to solve these problems. A line following portable robot is installed under the trolley to lead the users to the items’ location that they plan to purchase in the supermarket. This paper presents the hardware and software design of the portable robot. The result of the testing on the used sensors like ultrasonic and line sensors are presented. Lastly, the graphical user interface of Android application during the shopping trolley in operation is explained